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Dayanand S, K R V, T R, Shirur YJM, Munavalli JR. Low Power High Speed Vedic Techniques in Recent VLSI Design – A Survey. pices [Internet]. 2020Oct.5 [cited 2024Nov.22];4(6):147-56. Available from: http://pices-journal.com/ojs/index.php/pices/article/view/226