DAYANAND, S.; K R, V.; T, R.; SHIRUR, Y. J. M.; MUNAVALLI, J. R. Low Power High Speed Vedic Techniques in Recent VLSI Design – A Survey. Perspectives in Communication, Embedded-systems and Signal-processing - PiCES, [S. l.], v. 4, n. 6, p. 147-156, 2020. DOI: 10.5281/zenodo.4247825. Disponível em: http://pices-journal.com/ojs/index.php/pices/article/view/226. Acesso em: 22 nov. 2024.