[1]
Ramesh, A.V., Kumar, A.R., Iyengar, A.S. and B, L.Y. 2020. Implementation and Design of FIR Filters using Verilog HDL and FPGA. Perspectives in Communication, Embedded-systems and Signal-processing - PiCES. 4, 5 (Sep. 2020), 85-88. DOI:https://doi.org/10.5281/zenodo.4018834.