VLSI implementation of AES Encryption/Decryption Algorithm using FPGA

Abstract

AES stands for Advanced Encryption Standard and it is very efficient algorithm available today. Depending upon the key length it will become more efficient, 3 key length options supported here, viz. 128,192 bit and 256 bit key length. We generate encrypted data from the raw data bits and the same encrypted data is passed to the decryption blocks to recover the data back. From the hardware perspective, Field Programmable Gate Array (FPGA) is being used for hardware implementations in encryption process. The design of AES will be carried out in MATLAB and verified. RTL coding done using Verilog HDL, Xilinx Spartan 3A FPGA will be used in implementation. Modelsim is used in simulation Function and Timing simulations. The design will be implemented as per VLSI Industry Standard FPGA flow.