Design and Stability Analysis of CNTFET Based SRAM Cell

Authors

  • Pooja B Urs GSSS Institute of Engineering and Technology for Women, Mysuru, Karnataka, India
  • Prajna Prajna GSSS Institute of Engineering and Technology for Women, Mysuru, Karnataka, India
  • H L Prakruthi GSSS Institute of Engineering and Technology for Women, Mysuru, Karnataka, India
  • Priyanka G Hegde GSSS Institute of Engineering and Technology for Women, Mysuru, Karnataka, India
  • V Bhagyalakshmi GSSS Institute of Engineering and Technology for Women, Mysuru, Karnataka, India

Keywords:

CNTFET, SRAM

Abstract

Electronic gadgets like computers usually rely on memory devices because the digital information must be stored in these memory devices. Among many memory devices available Static Random Access Memory (SRAM) is the most crucial one. Due to continuous scaling of CMOS technology, it limits the performance of 6T SRAM cell in terms of leakage power. So carbon nanotube field effect transistor (CNTFET) are widely studied as possible alternative. Verilog-A code of CNTFET based SRAM cell is simulated in Cadence Virtuoso Tool. Here the conventional 6T SRAM cell is compared with CNFET based SRAM cell.

Downloads

Download data is not yet available.

Downloads

Published

2017-09-05

How to Cite

[1]
P. B. Urs, P. Prajna, H. L. Prakruthi, P. G. Hegde, and V. Bhagyalakshmi, “Design and Stability Analysis of CNTFET Based SRAM Cell”, pices, vol. 1, no. 5, pp. 82-85, Sep. 2017.