Implementation of Decimator Filter in 5G system for Area and Power Optimization Using FPGA
Keywords:
5G systems, Baseband section, Sampling frequency, Spartan 3e FPGA, Area, PowerAbstract
One of the key components in the baseband section of a 5G system is the filter decimator unit. This unit helps to remove the excess bandwidth and reduce the sampling frequency of the given signal. The existing decimator filter works at higher frequency. As the power increases the frequency increases and vice-versa, this filter often consumes more power. Also, the area consumption is high. The main idea of the project is to modify the architecture of the decimator filter such that, it will consume lower area and power. The final architecture will be realized for Spartan 3e FPGA.
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Wei Hu, Chongwei Zheng, Yonghao Wang, Jing Liu; Cen Chen, Zeng Zeng. “A Novel Economical Design of Multistage Decimators for Low Latency Audio Applications”. 2020 IEEE 22nd International Conference on High Performance Computing and Communications; IEEE 18th International Conference on Smart City; IEEE 6th International Conference on Data Science and Systems (HPCC/SmartCity/DSS).
Dejan N Milic, Member IEEE A New Class of low Complexity Low Pass Multiplier Less Linear-Phase Special CIC FIR filters. IEEE Signal Processing Letters, 2014. 21(12):1511-1515.
Park S Multistage decimation filter design technique for high-resolution sigma-delta A/I) converters. IEEE-transactions on instrumentation and measurements,2019, 41(6) 868-87.
Bellanger M, Interpolation, Extrapolation and Reduction of Computation Speed in Digital Filters. IEEE Tran.acoust.Speech Signal Processing 1947,22(4):231-235.
David Ernesto Troncoso Romero, Miriam Guadalupe Cruz Jimenez, and Uwe Meyer Baese. An Alternative Data Path for the Cascaded Integrator & Comb Decimator. IEEE -crc decimator 2021.
Markeljan Fishta, Franco Fiori. By using a low-cost microcontroller, delta-sigma-modulated signals are decimated. IEEE- analog-to-digital converters, June 2021.
Divya Gautam, Kavita Khare, And Bhavana P. Shrivastava, A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization Technique. IEEE sample rate conversion filter for decimation with at passband, March 2021.
Gordana Jovanovic Dolecek, Design of Two-Stage Comb-Based Decimation Filter with High Aliasing Rejection and Low Passband Droop. IEEE design of comb-based decimation filter with a high aliasing rejection and low passband droop, September, 2021.
Fabian Hohn, Lars Nordström, Integrating Signals with High Sampling Rates for Transmission Line Protection in Digital Substations. VOL. 36, NO. 6, DECEMBER 2021.
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