A Survey on VLSI Implementation of Low Power, High Speed DAC

Authors

  • Dhanushree L Department of Electronics and Communication, Sapthagiri College of Engineering, Bengaluru
  • Parvathy Parvathy Department of Electronics and Communication, Sapthagiri College Of Engineering, Bengaluru
  • Lavanya R Department of Electronics and Communication, Sapthagiri College Of Engineering, Bengaluru
  • Sudha M S Department of Electronics and Communication, Sapthagiri College of Engineering, Bengaluru

Keywords:

DAC, R2R, Low Power, Current Steering, CMOS

Abstract

Digital to analog converters, are commonly used to convert digital data streams into analog audio signals, this conversion is important because it significantly increases the overall value of the system. There are many strategies that are already developed in the DAC (Digital to Analog) converter field to meet necessary requirements. The Low power Current Steering 6-bit counter and R-2R ladder Digital to Analog Converter are designed in this paper. In this the R-2R ladder network is  designed using only two Valued resistor R and 2R the switch is designed using NMOS and PMOS Transistors. This design is operated with low voltage by using DTMOS logic. This design aims to achieve less INL (integrated nonlinearity) of 0.3 and
DNL(differential nonlinearity) of 0.06. It consumes only 1V of power and it requires 10Ghz frequency. This entire DAC design is operated with the help of 180nm CMOS technique. 

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Published

2022-06-13

How to Cite

[1]
D. L, P. Parvathy, L. R, and S. M S, “A Survey on VLSI Implementation of Low Power, High Speed DAC”, pices, pp. 26-28, Jun. 2022.

Issue

2022: PiCES - Special Issue

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Articles

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