A 5G Based Demodulator On FPGA
DOI:
https://doi.org/10.5281/zenodo.5867741Keywords:
Demodulation, Phase error, Phase locked loop, 5G, BPSK modulationAbstract
In a digital communication system, demodulation is one of the key components. Often, during demodulation the problem of phase error arises, which has to be detected and corrected in order to get the right information. A phase locked loop is employed for the same. A BPSK modulation technique is used for modulating message signals in a 5G environment. The idea of the paper would be to develop a phase error detection & correction system, aiming at a low power & low area architecture. Both proposed and existing systems are implemented in Spartan 3E FPGA. Simulation is done in VHDL using Xilinx and MATLAB software.
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