Low Power High Speed Vedic Techniques in Recent VLSI Design – A Survey
DOI:
https://doi.org/10.5281/zenodo.4247825Keywords:
Vedic mathematics, VLSI, Nikhilam, Urdhva Tiryakbhyam, Yavadunam, Ekanyunena Purvena, AnurupyenaAbstract
Advancement in the Artificial Intelligence (AI) and Machine Learning (ML) has influenced complex designs to be integrated in Very Large-Scale Integration (VLSI) Design. Designers are concentrating on high speed and low power techniques to facilitate the needs of the technology requirements. In multiple AI applications, Digital Signal Processor is the building block, optimization of it may solve the issues related to computation of the data signal at faster rate consuming less power using Vedic mathematics. In this paper, a detailed review is made on recent applications of Vedic Mathematics in the domain of VLSI to yield novel design, efficient architecture for Squarer, Multiplier, Arithmetic unit, Cubic and divider circuits along with their crucial performance criteria. It is deduced that the use of Vedic Sutras in formulating algorithms for digital logic circuit design has led to simplified architecture and yielded higher speed, low power consumption and enhanced efficiency of operation.
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