Implementation and Design of FIR Filters using Verilog HDL and FPGA
DOI:
https://doi.org/10.5281/zenodo.4018834Keywords:
VLSI systems, Digital Filter, FIR filter, Linear phase, Impulse Response, MAC operation, FPGA kitAbstract
Digital filters play a major role in Very Large-Scale Integration Technology (VLSI), as most VLSI systems use addition as an integral operation. One such filter is FIR filter, whose basic implementation is achieved by adders. This paper mainly aims at designing a Moving Average 4-tap FIR filter using Verilog HDL and is implemented using Xilinx software and Spartan 6 FPGA kit with the concepts of Multiply and Accumulate (MAC) operation and convolution.
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Emmanuel S. Kolawole Warsame H. Ali, Penrose Cfie, John Fuller, C. Tolliver, Pamela Obiomon, “Design and Implementation of Low-pass, High-pass and Band- pass Finite Impulse Response (FIR) Filters using FPGA”, Circuits and Systems 2015, 6, 30–48, Published online February 2015 in SciRes.
S. Subathradevi and C. Vennila, “Delay Optimized Novel Architecture of FIR Filter using Clustered-Retimed MAC unit Cell for DSP Applications”, Natural Sciences Publishing Cor.Published online July 2017.
Sangram Patil , Prithviraj Patil , Indrajit Patil, Prof.Sachin Jadhav, “Implementation of FIR Filter using VLSI”, AESS Journal, October 2017. ISSN: 0975 – 6779.
Proakis & Manolakis, “Digital signal processing – Principles Algorithms & Applications”, 4th Edition, Pearson education, New Delhi, 2007. ISBN: 81-317-1000-9.
Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Pearson Education, Second Edition.
Bahram Rashidi, Farshad Mirzaei, Bahman Rashidi and Majid Pourormazd, “Low power FPGA Implementation of Digital FIR Filter based on Low Power Multiplexer Based Shift/Add Multiplier”, International Journal of Computer Theory and Engineering, 5(2), April 2013.
Ruan, A.W., Liao, Y.B. and Li, J.X. (2009) An ALU-Based Universal Architecture for FIR Filters. IEEE Proceedings of International Conference on communications, Circuits and Systems, Milpitas, July 2009, 1070-1073.
Panayiotis, P. (2005) Frequency Response of Filters. Rutgers University, New Brunswick.
Zhang Chi and Guo Li Li, “Design of FIR filter with Matlab and running on FPGA”, Applied Science and Technology. vol. 33, no. 6, pp.83, Jun. 2006.
P.P.Vaidyanathan, Multirate Systems and Filter Banks, Prentice-Hall, Englewood Cliffs, NJ, 1993.
S.Salivahanan, A. Vallavaraj, C. Gnanapriya, Digital Signal Processing, TMH/McGraw Hill International, 2007.
E.C. Ifeachor and B.W. Jervis, “Digital signal processing – A practical approach”, Second edition, Pearson, 2002.
Concurrent replication of active logic blocks: A core solution for online testing and logic space defragmentation in reconfigurable systems - Scientific Figure on Research Gate. Published online November 23, 2019.
Johny R. Johnson, Introduction to Digital Signal Processing, PHI, 2006.
Oppenheim & Schafer, “Discrete Time Signal Processing”, PHI, 2003.
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