Complex Multiplier Architectures on VLSI

Authors

  • Pragnya Patil Department of ECE, BNM Institute of Technology, Bengaluru, India
  • Subodh Kumar Panda Department of ECE, BNM Institute of Technology, Bengaluru, India

Keywords:

Multipliers, VLSI, Complex Numbers, FPGA, Booth, Modified Booth

Abstract

Complex number multipliers are the mainstay for Digital Signal Processing (DSP) algorithms and for many other scientific applications. Multipliers are the slowest elements in the system due to their circuit complexity. Hence, they play key role in deciding system’s performance. Thus, it is necessary to reduce the complexity of these operations at architectural level and can save the chip area and further speed and power parameters can be optimized. In this paper, literature survey of various papers related to Multipliers are carried out.

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Published

2020-05-05

How to Cite

[1]
P. Patil and S. K. Panda, “Complex Multiplier Architectures on VLSI”, pices, vol. 4, no. 1, pp. 1-3, May 2020.

Issue

Vol. 4 No. 1 (2020): Issue 1 - April 2020

Section

Articles

License

Copyright (c) 2020 Perspectives in Communication, Embedded-systems and Signal-processing - PiCES

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.