Designing of 4G Baseband Receiver Filter Decimator Module

Abstract

Filter decimator model is the most integral part of baseband wireless receivers. At the receiver an Intermediate Frequency (IF) signal is converted to Baseband signal. This conversion is done in three stages - mixing, decimation and filtering. Because of this reason, the architecture of the filter and decimator consumes more area and power. In this paper, an improvised architecture of filter and decimator has been presented. Modelsim software was used for implementation of the idea. The results suggest that the proposed model of the 4G receiver consumes less power and area than the existing method.